Behavioral network graph: unifying the domains of high-level and logic synthesis
暂无分享,去创建一个
[1] Joos Vandewalle,et al. Loop Optimization in Register-Transfer Scheduling for DSP-Systems , 1989, 26th ACM/IEEE Design Automation Conference.
[2] Richard L. Rudell. Tutorial: design of a logic synthesis system , 1996, 33rd Design Automation Conference Proceedings, 1996.
[3] Pierre G. Paulin,et al. Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Louise Trevillyan,et al. Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[5] Daniel Brand,et al. BooleDozer: Logic synthesis for ASICs , 1996, IBM J. Res. Dev..
[6] S. J. McFarland,et al. The value trace : a data base for automated digital design , 1978 .
[7] D. J. Allerton,et al. A graph-based silicon compiler for concurrent VLSI systems , 1988, [Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools.
[8] Richard L. Rudell. Design of a logic synthesis system (tutorial) , 1996, DAC 1996.
[9] Raul Camposano,et al. Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Louise Trevillyan,et al. Logic Synthesis Through Local Transformations , 1981, IBM J. Res. Dev..
[11] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.