论文信息 - Design of a Hybrid Column Segmented CMOS Image Sensor with an Artificial Intelligence Core and a Novel SRAM Readout Logic

Design of a Hybrid Column Segmented CMOS Image Sensor with an Artificial Intelligence Core and a Novel SRAM Readout Logic

In this paper, a hybrid column segmented CMOS image sensor (CIS) with an artificial intelligence (AI) core and a novel SRAM readout circuit is presented. To obtain a high performance and high speed column parallel CIS, each column is segmented into two parts: the first one is a DC reference voltage generator with a bandgap reference circuit, and the second one is a fine ramp generator with an AI core and a digital-to-analog converter (DAC). Further, a novel SRAM readout circuit to improve the speed of digital block is also discussed. Based on this hybrid column segmented technique, excellent measured results are reported. With a 90nm backside illumination (BSI) technology, a 12-bit resolution image quality and 407uW power consumption per column are satisfied.

Minkyu Song | Keunyeol Park | Cheeyoung Lee | Soo Youn Kim

[1] T. Watabe,et al. A 33 Mpixel , 120 fps CMOS Image Sensor for UDTV Application with Two-stage Column-Parallel Cyclic ADCs , .

[2] Fukushima Noriyuki,et al. A 17.7Mpixel 120fps CMOS Image Sensor with 34.8Gb/s Readout , 2011 .

[3] Minho Kwon,et al. A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture , 2011, IEEE Journal of Solid-State Circuits.