Time-Domain Macromodels for

This paper presents a method of obtaining time- domain macromodels of VLSI interconnection networks for cir- cuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, with- out significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incor- porating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and gen- erality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects.

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