Design of Arithmetic Circuits Using Resonant-Tunneling Diodes and Threshold Logic

This paper describes the design of arithmetic circuits based on hybrid integrated resonant tunneling diodes and heterostructure eld-e ect transistors. The key components are depth-2 parallel counters consisting of multiple terminal threshold gates. In particular, we propose a novel parallel addition scheme by combining threshold logic and systolic VLSI-algorithms for bit-level computations. The approach is motivated by the demand for locally interconnected circuit modules to solve the wiring problem in nanoelectronic circuits.

[1]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[2]  Stamatis Vassiliadis,et al.  δ-Bit serial binary addition with linear threshold networks , 1996, J. VLSI Signal Process..

[3]  Lutz J. Micheel,et al.  Multiple-valued logic computation circuits using micro- and nanoelectronic devices , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[4]  Eiiti Wada,et al.  Esaki Diode High-Speed Logical Circuits , 1960, IRE Trans. Electron. Comput..

[5]  Earl E. Swartzlander Parallel Counters , 1973, IEEE Transactions on Computers.

[6]  John V. McCanny,et al.  Implementation of signal processing functions using 1-bit systolic arrays , 1982 .

[7]  J.P.A. van der Wagt,et al.  RTD/HFET low standby power SRAM gain cell , 1998, IEEE Electron Device Letters.

[8]  S. Cotofana,et al.  Block Save Addition with Telescopic SumsS , 1995 .

[9]  W.C.B. Peatman,et al.  Novel resonant tunneling transistor with high transconductance at room temperature , 1994, IEEE Electron Device Letters.

[10]  M. G. Ancona Systolic processor designs using single-electron digital circuits , 1996 .

[11]  Bernard Chazelle,et al.  Census functions: An approach to VLSI upper bounds , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[12]  T. Adachihara,et al.  Logic circuits using resonant-tunneling hot electron transistors (RHETs) , 1991, [1991] GaAs IC Symposium Technical Digest.

[13]  Karl Goser,et al.  Functional Integration of Parallel Counters Based on Quantum-Effect Devices , 1997 .

[14]  C. Pacha,et al.  Aspects of systems and circuits for nanoelectronics , 1997, Proc. IEEE.

[15]  K. Maezawa,et al.  InP-based high-performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devices , 1996, IEEE Electron Device Letters.

[16]  Gary H. Bernstein,et al.  12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates , 1997, IEEE J. Solid State Circuits.

[17]  A. Seabaugh,et al.  Coupled-quantum-well field-effect resonant tunneling transistor for multi-valued logic/memory applications , 1994 .

[18]  L. Kuhnel Optimal purely systolic addition , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[19]  William H. Kautz The Realization of Symmetric Switching Functions with Linear-Input Logical Elements , 1961, IRE Trans. Electron. Comput..