Power calculation for CMOS gate arrays

This paper describes a new procedure to calculate the power consumption of VLSI CMOS Gate Arrays. The system is based on a pre-defined power model library describing the physical behavior of all macros in Motorola's cell library in terms of power dissipation. The short circuit current of the complementary transistors is taken into account. For a specific design first the required circuit data are calculated and then the toggle frequencies for all macro instances are determined through logical simulation. Using this data the power calculator POWCAL derives the total power consumption of every instance and for the whole design automatically. The power can be calculated for Motorola's HDCMOS and H4C technologies dependent on the supply voltage, the die temperature and the process.<<ETX>>