Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses

Power consumption and delay are two of the most important constraints in current-day on-chip bus design. The two major sources of dynamic power dissipation on a bus are the self capacitance and the coupling capacitance. As technology scales, the interconnect resistance increases due to shrinking wire-width. At the same time, spacing between the interconnects decreases resulting in an increase in the coupling capacitance. This, in turn, leads to stronger crosstalk effects between the interconnects. In Deep SubMicron technology the coupling capacitance exceeds the self capacitance, which, in turn, cause more power consumption and delay on the bus. Recently, the interest has also shifted to minimizing peak power dissipation. The reason being that higher peak power leads to an undesired increase in switching noise, metal electromigration problems and operationinduced variations due to non-uniform temperature on the die. Thus, minimizing power consumption and delay are the most important design objectives for on-chip buses. Several bus encoding schemes have been proposed in the literature for reducing crosstalk. Most of these encoding techniques use spatial redundancy that requires additional transmission wires on the bus. In this paper, a new temporal encoding scheme is proposed, which uses self-shielding memory-less codes to completely eliminate worst-case crosstalk effects and hence significantly minimizes power consumption and delay of the bus. A major advantage of the proposed temporal redundancy based encoding scheme is the reduction in the number of wires of the on-chip bus. This reduction facilitates extra spacing between the bus wires, when compared with the normal bus, for a given area. This, in turn, leads to reduced crosstalk effects between the wires. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks. The experimental results, when compared to the transmission over a normal bus, show that on an average the proposed technique leads to a reduction in the peak-power consumption by 51% (28%), 51% (29%) and 52% (30%) in the data (address) bus for 90nm, 65nm and 45nm technologies, respectively. For a bus length of 10mm the proposed technique also achieves 17%, 31% and 37% reduction in the bus delay for 90nm, 65nm and 45nm technologies, respectively, when compared to what is incurred by the data transmission on a normal bus.