Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented These solutions agree with AS/X circuit simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects become more significant as compared to an RC dominated interconnect.

[1]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[3]  Gerard V. Kopcsay,et al.  High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..

[4]  V. Semenov,et al.  RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.

[5]  Erich Barke,et al.  Line-to-ground capacitance calculation for VLSI: a comparison , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Robert H. Dennard,et al.  Modeling and characterization of long on-chip interconnections for high-performance microprocessors , 1995, IBM Journal of Research and Development.

[7]  D. A. Priore.  Inductance on silicon for sub-micron CMOS VLSI , 1993, Symposium 1993 on VLSI Circuits.

[8]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[9]  W. R. Eisenstadt,et al.  High-speed VLSI interconnect modeling based on S-parameter measurements , 1993 .

[10]  R. J. Antinone,et al.  The modeling of resistive interconnects for integrated circuits , 1983 .

[11]  Lawrence N. Dworsky,et al.  Modern Transmission Line Theory and Applications , 1980 .

[12]  Allen Taflove,et al.  FD-TD modeling of digital signal propagation in 3-D circuits with passive and active loads , 1994 .

[13]  J. Torres,et al.  Advanced copper interconnections for silicon CMOS technologies , 1995 .

[14]  Denis B. Jarvis.  The Effects of Interconnections on High-Speed Logic Circuits , 1963, IEEE Trans. Electron. Comput..

[15]  Eby G. Friedman,et al.  A system for critical path analysis based on back annotation and distributed interconnect impedance models , 1988 .

[16]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[17]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[18]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[19]  Eby G. Friedman,et al.  Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load , 1996 .

[20]  P. Yang,et al.  Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.

[21]  Masakazu Shoji,et al.  High-Speed Digital Circuits , 1996 .

[22]  Srinivasa Vemuru,et al.  Short-circuit power dissipation estimation for cmos logic gates , 1994 .

[23]  Mark Horowitz,et al.  Resistance Extraction from Mask Layout Data , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[25]  Eby G. Friedman,et al.  Ramp Input Response of RC Tree Networks , 1996 .

[26]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[27]  S. Bothra,et al.  Analysis of the effects of scaling on interconnect delay in ULSI circuits , 1993 .

[28]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.