Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS

This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.

[1]  Tughrul Arslan,et al.  A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems , 2005, Proceedings 2005 IEEE International SOC Conference.

[2]  Rolf Johannesson,et al.  Fundamentals of Convolutional Coding , 1999 .

[3]  Ran-Hong Yan,et al.  A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[4]  T. G. Noll,et al.  Study of heterogeneous and reconfigurable architectures in the communication domain , 2003 .

[5]  Yiqun Zhu,et al.  Reconfigurable Viterbi decoding using a new ACS pipelining technique , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[6]  John B. Anderson,et al.  Coded Modulation Systems , 2003 .

[7]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[8]  ScienceDirect.  Microprocessors and microsystems , 1978 .

[9]  Teresa H. Meng,et al.  A 140-Mb/s, 32-state, radix-4 Viterbi decoder , 1992 .

[10]  John B. Anderson,et al.  Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  G. Ungerboeck,et al.  Trellis-coded modulation with redundant signal sets Part II: State of the art , 1987, IEEE Communications Magazine.

[12]  Paola Bisaglia,et al.  Simplified soft-output demapper for binary interleaved COFDM with application to HIPERLAN/2 , 2002, 2002 IEEE International Conference on Communications. Conference Proceedings. ICC 2002 (Cat. No.02CH37333).

[13]  John M. Cioffi,et al.  A programmable codec design for trellis coded modulation , 1997, GLOBECOM 97. IEEE Global Telecommunications Conference. Conference Record.

[14]  G. Ungerboeck,et al.  Trellis-coded modulation with redundant signal sets Part I: Introduction , 1987, IEEE Communications Magazine.

[15]  John B. Anderson,et al.  Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  Jr. G. Forney,et al.  Viterbi Algorithm , 1973, Encyclopedia of Machine Learning.

[17]  D. E. Hocevar,et al.  Achieving flexibility in a Viterbi decoder DSP coprocessor , 2000, Vehicular Technology Conference Fall 2000. IEEE VTS Fall VTC2000. 52nd Vehicular Technology Conference (Cat. No.00CH37152).

[18]  J. Karaoguz,et al.  High-rate wireless personal area networks , 2001, IEEE Commun. Mag..

[19]  John B. Anderson,et al.  A simplified computational kernel for trellis-based decoding , 2004, IEEE Communications Letters.

[20]  Dennis Goeckel,et al.  A reconfigurable, power-efficient adaptive Viterbi decoder , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  J.R. Cavallaro,et al.  A reconfigurable Viterbi decoder architecture , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[22]  Joseph R. Cavallaro,et al.  Viturbo: a reconfigurable architecture for Viterbi and turbo decoding , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[23]  Yasuo Hirata,et al.  High-Rate Punctured Convolutional Codes for Soft Decision Viterbi Decoding , 1984, IEEE Trans. Commun..

[24]  Kouhei Yamamoto,et al.  High-performance programmable SISO decoder VLSI implementation for decoding turbo codes , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).