BiCMOS—Circuits and Technology

BiCMOS which combines CMOS and bipolar circuits for high performance together with high density and low power has been recognised to be the emerging silicon technology. This paper brings out the compatibility of present day VLSI CMOS and bipolar technologies and discusses the orientations necessary for optimization of devices and circuits involved. Simulation results of a few simple BiCMOS circuits have been presented. Attention has been focussed on application areas where BiCMOS would be extremely useful.

[1]  H. Momose,et al.  A high-speed 64K CMOS RAM with bipolar sense amplifiers , 1984, IEEE Journal of Solid-State Circuits.

[2]  B. Hoefflinger,et al.  A compatible NMOS, CMOS metal gate process , 1978, IEEE Transactions on Electron Devices.

[3]  G. P. Li,et al.  A 1.0-ns 5-kbit ECL RAM , 1986 .

[4]  A. Bhattacharyya,et al.  A 20 K CMOS array with 200-ps gate delay , 1988 .

[5]  Masanori Odaka,et al.  13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology , 1986 .

[6]  T. Yamaguchi,et al.  Process integration and device performance of a submicrometer BiCMOS with 16-GHz f/sub t/ double poly-bipolar devices , 1989 .

[7]  Tran Van Muoi,et al.  Integrated circuits for a 200 Mbit/s fiber-optic link , 1986 .

[8]  H.S. Moscovitz,et al.  A 32-bit VLSI digital signal processor , 1985, IEEE Journal of Solid-State Circuits.

[9]  Kiyoo Itoh,et al.  An experimental 1-Mbit BiCMOS DRAM , 1987 .

[10]  T. Okabe,et al.  An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI , 1985, IEEE Transactions on Electron Devices.

[11]  B. Santo.  BiCMOS circuitry: the best of both worlds , 1989, IEEE Spectrum.

[12]  Bruce A. Wooley,et al.  A 4-ns 4K*1-bit two-port BiCMOS SRAM , 1988 .

[13]  Douglas D. Smith,et al.  A 12-ns ECL I/O 256 K*1-bit SRAM using a 1- mu m BiCMOS technology , 1988 .

[14]  B. Carney,et al.  A high density BiCMOS direct drive array , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[15]  I. Masuda,et al.  Perspective on BiCMOS VLSIs , 1988 .

[16]  M. Kohara,et al.  A bipolar 18K-gate variable size cell masterslice , 1986 .

[17]  K.K. O,et al.  A 2- mu m BiCMOS process utilizing selective epitaxy , 1988, IEEE Electron Device Letters.

[18]  B. Peetz,et al.  An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold , 1986 .

[19]  K.K. O,et al.  A bipolar structure with semi-dielectric device isolation by selective epitaxial growth , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[20]  J.N. Babanezhad,et al.  A 20-V four-quadrant CMOS analog multiplier , 1985, IEEE Journal of Solid-State Circuits.

[21]  Y. Takasaki,et al.  A single-chip three-level regenerator IC for high-speed optical transmission systems applying duo-binary coding schemes , 1986 .

[22]  G. P. Rosseel,et al.  Influence of device parameters on the switching speed of BiCMOS buffers , 1989 .

[23]  R. Reimann,et al.  A 4:1 time-division multiplexer IC for bit rates up to 6 Gbit/s based on a standard bipolar technology , 1986 .

[24]  H. Momose,et al.  1.0-/spl mu/m n-Well CMOS/Bipolar Technology , 1985, IEEE Journal of Solid-State Circuits.

[25]  H. Fritzsche,et al.  A 150-ps 9000-gate ECL masterslice , 1985, IEEE Journal of Solid-State Circuits.

[27]  M. Okabe,et al.  An ECL 5000-gate gate array with 190-ps gate delay , 1986 .

[28]  J.L. Van Meerbergen,et al.  A 2-/spl mu/m CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank , 1985, IEEE Journal of Solid-State Circuits.

[29]  Takashi Hotta,et al.  CMOS/bipolar circuits for 60-MHz digital processing , 1986 .

[30]  C. Volz,et al.  A high-performance bipolar/CMOS process-CIT2 , 1988 .

[31]  Ashwin H. Shah,et al.  An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability , 1988 .

[32]  N. Yokozawa,et al.  A 500-MHz 8-bit D/A converter , 1985, IEEE Journal of Solid-State Circuits.

[33]  B. Hoefflinger,et al.  A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems , 1979, IEEE Transactions on Electron Devices.