Low-power multiplier design with row and column bypassing

Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2-dimensional bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the power dissipation with only 15% hardware overhead on the average for 4×4, 8×8 and 16×16 multipliers.

[1]  Sying-Jyan Wang,et al.  Low-power parallel multiplier with column bypassing , 2005 .

[2]  Tat Chee Ave.  HIGH PERFORMANCE ADDER CELL FOR LOW POWER PIPELINED MULTIPLIER , 1996 .

[3]  Kiyoung Choi,et al.  Dynamic operand interchange for low power , 1997 .

[4]  Koji Inoue,et al.  Multiplier energy reduction through bypassing of partial products , 2002, Asia-Pacific Conference on Circuits and Systems.

[5]  Kiyoung Choi,et al.  Power minimization of functional units by partially guarded computation , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[6]  Chua-Chin Wang,et al.  A low-power 2D bypassing multiplier using 0.35 μm CMOS technology , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[7]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[8]  Keikichi Tamaru,et al.  A comparative study of switching activity reduction techniques for design of low-power multipliers , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.