Single exposure is still alive: gate patterning at 45nm technology node

A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm technology node. They consist mainly of the introduction of a new software for optical proximity correction, the introduction of model based process window correction, the switch to model based etch proximity correction, and support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.