Combinational and sequential mapping with priority cuts

An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids the hurdle of computing all K-input cuts while preserving the quality of the results, in terms of area and depth. The memory and runtime of the proposed algorithm are linear in circuit size and quite affordable even for large industrial designs. For example, computing a good quality 6-LUT mapping of an AIG with 1 M nodes takes 150 Mb of RAM and 1 minute on a typical laptop. An extension of the algorithm allows for sequential mapping, which searches the combined space of all possible mappings and retimings. This leads to an 18-22% improvement in depth with a 3-5% LOT count penalty, compared to combinational mapping followed by retiming.

[1]  Jason Cong,et al.  On area/depth trade-off in LUT-based FPGA technology mapping , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Yen-Tai Lai,et al.  An efficient algorithm for finding the minimal-area FPGA technology mapping , 2005, TODE.

[3]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[4]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Stephen Dean Brown,et al.  Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Jason Cong,et al.  Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[7]  Robert K. Brayton,et al.  Integrating Logic Synthesis, Technology Mapping, and Retiming , 2005 .

[8]  Robert K. Brayton,et al.  Improvements to Technology Mapping for LUT-Based FPGAs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Jason Cong,et al.  Cut ranking and pruning: enabling a general and efficient FPGA mapping solution , 1999, FPGA '99.

[10]  Majid Sarrafzadeh,et al.  Complexity of the lookup-table minimization problem for FPGA technology mapping , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Peichen Pan,et al.  A new retiming-based technology mapping algorithm for LUT-based FPGAs , 1998, FPGA '98.

[12]  Alan Mishchenko,et al.  Applying Logic Synthesis for Speeding Up SAT , 2007, SAT.

[13]  Stephen Dean Brown,et al.  Incremental retiming for FPGA physical synthesis , 2005, Proceedings. 42nd Design Automation Conference, 2005..