LFSR-Based Deterministic TPG for Two-Pattern Testing

This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.

[1]  Karl Fuchs,et al.  A BIST approach to delay fault testing with reduced test length , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[2]  Patrick Girard,et al.  An optimized BIST test pattern generator for delay testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[3]  Edward J. McCluskey,et al.  TWO-PATTERN TEST CAPABILITIES OF AUTONOMOUS TPG CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[4]  C.-J. Richard Shi,et al.  Cluster-cover: a theoretical framework for a class of VLSI-CAD optimization problems , 1998, TODE.

[5]  Kurt Keutzer,et al.  An algorithmic approach to optimizing fault coverage for BIST logic synthesis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[7]  Yervant Zorian,et al.  On the generation of pseudo-deterministic two-patterns test sequence with LFSRs , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[8]  Constantin Halatsis,et al.  Accumulator-based BIST approach for stuck-open and delay fault testing , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[9]  Xiaowei Li,et al.  Exploiting BIST approach for two-pattern testing , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[10]  D. Michael Miller,et al.  BIST generators for sequential faults , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[11]  Corot W. Starke,et al.  Built-In Test for CMOS Circuits , 1984, ITC.

[12]  Slawomir Pilarski,et al.  BIST and delay fault detection , 1993, Proceedings of IEEE International Test Conference - (ITC).

[13]  Sandeep K. Gupta,et al.  BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms , 1996, IEEE Trans. Computers.

[14]  Solomon W. Golomb,et al.  Shift Register Sequences , 1981 .