FPGA based EBCOT architecture for JPEG 2000

In this paper a high speed FPGA based implementation of Embedded Block Coding with Optimized Truncation (EBCOT) algorithm used in JPEG 2000 has been proposed and implemented. The context formation engine used in EBCOT is analyzed and an architecture based on parallel processing of the three coding passes is proposed. The architecture is coded in VHDL and the design is targeted to Xilinx Virtex II FPGA family. When implemented on a XC2V1000 device, the design performs at 56 MHz after place and route. Simulation results show that the design can process a 512/spl times/512 image in less than 0.03 seconds and the processing time is reduced by more than 75% compared to sample based implementation and by more than 34% compared to the best architecture known.