Remote TSN Frame Encapsulation by means of FPGA

TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in the Industry 4.0. Field buses are not capable of providing neither connection for industry 4.0 IoT (Internet of Things) nor compatibility between different manufacturers. On the other hand, Ethernet is not able to ensure real-time. On the contrary, TSN guarantees real-time transmission, IoT and compatibility between devices. However, adapting to frequently changing needs makes TSN protocol evolve continuously. For this reason, devices for TSN analysis, such as PCs or not advanced frame analysis equipment are not able to process TSN packets at the speed that standard advances, discarding them as wrong frames. The integration of a System on Chip (SoC) that contains an FPGA (Field Programmable Gate Array) and a microcontroller, with capacity for reconfiguration and monitoring of the frames in the protocol, would be an ideal solution to this problem. This paper describes how to encapsulate TSN frames in Ethernet packets using an FPGA. Such Ethernet frames can subsequently be decapsulated, i.e. in a PC, and thus enable analysing TSN traffic in nonspecialized devices.