A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier

In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

[1]  Minho Kwon,et al.  A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture , 2011, IEEE Journal of Solid-State Circuits.

[2]  I. Takayanagi,et al.  A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor , 2005, IEEE Journal of Solid-State Circuits.

[3]  S. Watanabe,et al.  A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change , 2006, IEEE Journal of Solid-State Circuits.

[4]  Woodward Yang,et al.  An integrated 800/spl times/600 CMOS imaging system , 1999 .

[5]  Gunhee Han,et al.  CMOS image sensor with analog gamma correction using nonlinear single-slope ADC , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[6]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[7]  H. S. Wolff,et al.  iRun: Horizontal and Vertical Shape of a Region-Based Graph Compression , 2022, Sensors.

[8]  Takayoshi Yamada,et al.  A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Eric R. Fossum,et al.  A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor , 2003 .

[10]  Youngcheol Chae,et al.  A Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors , 2014, Sensors.

[11]  G. Han,et al.  High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers , 2007 .

[12]  M.F. Snoeij,et al.  Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors , 2007, IEEE Journal of Solid-State Circuits.

[13]  F. Koga,et al.  A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor , 2012 .

[14]  T. Watabe,et al.  A 33 Mpixel , 120 fps CMOS Image Sensor for UDTV Application with Two-stage Column-Parallel Cyclic ADCs , .

[15]  Gunhee Han,et al.  Noise Analysis and Simulation Method for a Single-Slope ADC With CDS in a CMOS Image Sensor , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  S. Watanabe,et al.  A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[17]  A. Suzuki,et al.  High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[18]  Seog-Heon Ham,et al.  A new Correlated Double Sampling and Single slope ADC circuit for CMOS Image Sensors , 2004 .

[19]  Kwangsoo Kim,et al.  A VGA CMOS Image Sensor with 11-bit column parallel single-slope ADCs , 2010, 2010 International SoC Design Conference.

[20]  M.F. Snoeij,et al.  A CMOS Imager With Column-Level ADC Using Dynamic Column Fixed-Pattern Noise Reduction , 2006, IEEE Journal of Solid-State Circuits.

[21]  T. Arakawa,et al.  A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).