Loop for Wireless Implantable Biomedical Devices

An ultra-low-power, low-voltage frequency synthe­ sizer designed for implantable biomedical devices is presented. Several design techniques are employed to address the issues in ultra-low voltage design, including the dynamic threshold-voltag e for a drain-switching charge pump and dual resistor-varacto r tuning for a ring-based voltage control oscillator . Moreover, three automatic calibration circuits are embedded to compensate the performance deviation due to process-voltage- temper �ture (PVT) variations. Designed in 0.13-J-tm CMOS technology wIth a power supply of 0.5 V, the PLL consumes 370 J-t W with a phase noise of -104 dBclHz at 1 MHz offset.

[1]  Kiat Seng Yeo,et al.  Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler , 2006, IEEE Transactions on Microwave Theory and Techniques.

[2]  Zhigong Wang,et al.  A high-performance CMOS charge-pump for phase-locked loops , 2008, 2008 International Conference on Microwave and Millimeter Wave Technology.

[3]  Wei-Bin Yang,et al.  Designing ultra-low voltage PLL Using a bulk-driven technique , 2009, 2009 Proceedings of ESSCIRC.

[4]  W.A.M. Van Noije,et al.  A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) , 1999, IEEE J. Solid State Circuits.

[5]  Peter R. Kinget,et al.  A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications , 2010, IEEE Journal of Solid-State Circuits.