Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method

Increasing leakage current makes single-threshold IDDQ testing ineffective for differentiating defective and detect-free chips. Quiescent-signal analysis is a new detection and diagnosis technique that uses IDDQ measurement at multiple chip supply ports, reducing the leakage component in each measurement and significantly improving detection of subtle detects. In this article, we apply linear regression analysis and a new technique called ellipse analysis to the data collected from a set of 12 test chips to illustrate QSA's defect detection capabilities and limitations. The design permits control over the magnitude of the emulated-defect current and the leakage current

[1]  James F. Plusquellic,et al.  Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement , 2004, ITC.

[2]  Chintan Patel,et al.  A Current Ratio Model for Defect Diagnosis using Quiescent Signal Analysis , 2002 .

[3]  Dhruva Acharyya,et al.  Hardware results demonstrating defect detection using power supply signal measurements , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[4]  James F. Plusquellic.  IC Diagnosis Using Multiple Supply Pad IDDQs , 2001, IEEE Des. Test Comput..

[5]  Claude Thibeault.  On the comparison of /spl Delta/I/sub DDQ/ and I/sub DDQ/ testing , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[6]  D. M. H. Walker,et al.  Neighbor current ratio (NCR): a new metric for I/sub DDQ/ data analysis , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[7]  James F. Plusquellic,et al.  A process and technology-tolerant I/sub DDQ/ method for IC diagnosis , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[8]  Dhruva Acharyya,et al.  Hardware Results Demonstrating Defect Localization Using Power Supply Signal Measurements , .

[9]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Claude Thibeault.  On the Comparison of IDDQ and IDDQ Testing , 1999, VTS.

[11]  Anura P. Jayasumana,et al.  Clustering based techniques for I/sub DDQ/ testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[12]  A.D. Singh.  A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[13]  James McNames,et al.  Variance reduction using wafer patterns in I/sub ddQ/ data , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[14]  J. Plusquellic,et al.  Defect detection under realistic leakage models using multiple I/sub DDQ/ measurements , 2004, 2004 International Conferce on Test.

[15]  D. M. H. Walker,et al.  Improved wafer-level spatial analysis for I/sub DDQ/ limit setting , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[17]  Dhruva Acharyya,et al.  Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids , 2003, J. Electron. Test..

[18]  Pramodchandran N. Variyam.  Increasing the IDDQ test resolution using current prediction , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).