Improving utilization of reconfigurable resources using two-dimensional compaction

Abstract Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the reconfigurable chip. Area management is a very important issue which highly affect the utilization of the chip and hence the performance. This paper focuses on a major aspect of moving running tasks to free space for new incoming tasks (compaction). We study the effect of compacting running tasks to free more contiguous space on the system performance. First, we introduce a straightforward compaction strategy called Blind compaction. We use its performance as a reference to measure the performance of other compaction algorithms. Then we propose a two-dimensional compaction algorithm called one-corner compaction. This algorithm runs with respect to one chip corner. We further extend this algorithm to the four corners of the chip and introduce the four-corners compaction algorithm. Finally, we compare the performance of these algorithms with some existing compaction strategies: Brebner, G. and Diessel, O. (Proceedings of the 11th international workshop on field programmable gate arrays (FPL), pp. 182–191, 2001); Diesel, O. and ElGindy, H. (Proceedings of the 5th Australasian conference on parallel and real-time systems (PART), pp. 191–200, 1998); Diesel, O., et al. (IEE proceedings on computers and digital techniques, vol. 147, pp. 181–188, 2000). The simulation results show improvement in average task allocation time when using the four-corners compaction algorithm by 15% and in chip utilization by 16% over the Blind compaction. These results outperform the existing strategies.