Single-ended structure sense-amplifier-based flip-flop for low-power systems

A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive post-layout simulations.

[1]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[2]  Mototsugu Hamada,et al.  Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Davide De Caro,et al.  A novel high-speed sense-amplifier-based flip-flop , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[5]  Lee-Sup Kim,et al.  A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme , 1994 .