High throughput multi-code LDPC encoder for CCSDS standard

A high throughput encoder based on Recursive Convolutional Encoder (RCE) circuits is designed for multi-code Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of CCSDS standard. The use of system registers is reduced by employing a parallel RCE circuit structure; by configuring these parallel RCE circuit structures, the encoder can support multiple patterns and code rates. The FPGA implementation results show that the design method can be implemented based on the Xilinx VC690T chip, and its normalized registers and LUTs are reduced by 39.4% and 24.4%, respectively, compared with the existing solutions.