A low power low noise current starved CMOS VCO for PLL

In this article an ultra low power, low phase noise current starved CMOS VCO are proposed. This CSVCO is applicable for PLL application such as in, clock generation and recovery, frequency synthesizer for cell phones, fast locking in digital aid circuits etc. This proposed circuits area and power consumptions are very less and compatible for PLL applications. It demonstrates the superlative performance of the CSVCO. Transient response and phase noise analysis is performed and after simulation the phase noise at 1MHz is -104.0dBc/Hz with supply voltage of 1 V. It is performed using cadence virtuoso gpdk045 nm CMOS technology.

[1]  S. Verma,et al.  A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis , 2004, IEEE Journal of Solid-State Circuits.

[2]  Ganapati Panda,et al.  A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO , 2014, IEEE Transactions on Semiconductor Manufacturing.

[3]  Huihua Liu,et al.  Design of low phase noise and fast locking PLL frequency synthesizer , 2011, 2011 International Conference on Electric Information and Control Engineering.

[4]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[5]  S. Gambini,et al.  A 52 $\mu$ W Wake-Up Receiver With $-$ 72 dBm Sensitivity Using an Uncertain-IF Architecture , 2009, IEEE Journal of Solid-State Circuits.

[6]  Franziska Hoffmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[7]  Vrushali G Nasre,et al.  A Performance Comparison of Current Starved VCO and Source Coupled VCO for PLL in 0 . 18 μ m CMOS Process , 2012 .

[8]  M Kraemer,et al.  A High Efficiency Differential 60 GHz VCO in a 65 nm CMOS Technology for WSN Applications , 2011, IEEE Microwave and Wireless Components Letters.

[9]  Nilesh D. Patel,et al.  Phase Frequency Detector and Charge Pump For DPLL Using 0.18µm CMOS Technology , 2013 .

[10]  Pei-Kang Tsai,et al.  Integration of Current-Reused VCO and Frequency Tripler for 24-GHz Low-Power Phase-Locked Loop Applications , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.