On Compacting Test Response Data Containing Unknown Values
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[1] Subhasish Mitra,et al. X-compact: an efficient response compaction technique for test cost reduction , 2002, Proceedings. International Test Conference.
[2] J.H. Patel,et al. Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[3] Nur A. Touba,et al. Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[4] Janak H. Patel,et al. Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).
[5] Hans-Joachim Wunderlich,et al. Tailoring ATPG for embedded testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[6] Irith Pomeranz,et al. On output response compression in the presence of unknown output values , 2002, DAC '02.
[7] Nilanjan Mukherjee,et al. Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.
[8] Sudhakar M. Reddy,et al. Convolutional compaction of test responses , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[9] Nur A. Touba,et al. Synthesis of zero-aliasing elementary-tree space compactors , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[10] Brion L. Keller,et al. OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[11] Ajay Khoche,et al. Packet-based input test data compression techniques , 2002, Proceedings. International Test Conference.
[12] Alex Orailoglu,et al. Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[13] Irith Pomeranz,et al. COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[15] Mark G. Karpovsky,et al. Testing Computer Hardware through Data Compression in Space and Time , 1983, ITC.
[16] B. Koneman,et al. LFSR-Coded Test Patterns for Scan Designs , 1993 .
[17] Irith Pomeranz,et al. On test data volume reduction for multiple scan chain designs , 2003, TODE.
[18] Janak H. Patel,et al. Application of Saluja-Karpovsky compactors to test responses with many unknowns , 2003, Proceedings. 21st VLSI Test Symposium, 2003..