Firefly: illuminating future network-on-chip with nanophotonics

Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the increasing number of cores. Recent advances in silicon nanophotonics create new opportunities for on-chip networks. To efficiently exploit the benefits of nanophotonics, we propose Firefly - a hybrid, hierarchical network architecture. Firefly consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using nanophotonics - exploiting the benefits of electrical signaling for short, local communication while nanophotonics is used only for global communication to realize an efficient on-chip network. Crossbar architecture is used for inter-cluster communication. However, to avoid global arbitration, the crossbar is partitioned into multiple, logical crossbars and their arbitration is localized. Our evaluations show that Firefly improves the performance by up to 57% compared to an all-electrical concentrated mesh (CMESH) topology on adversarial traffic patterns and up to 54% compared to an all-optical crossbar (OP XBAR) on traffic patterns with locality. If the energy-delay-product is compared, Firefly improves the efficiency of the on-chip network by up to 51% and 38% compared to CMESH and OP XBAR, respectively.

[1]  Luca P. Carloni,et al.  The Case for Low-Power Photonic Networks on Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[2]  Nan Jiang,et al.  Indirect adaptive routing on large scale interconnection networks , 2009, ISCA '09.

[3]  Y. Vlasov,et al.  Losses in single-mode silicon-on-insulator strip waveguides and bends. , 2004, Optics express.

[4]  Niraj K. Jha,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007, ICCD.

[5]  Berkin Özisikyilmaz,et al.  MineBench: A Benchmark Suite for Data Mining Workloads , 2006, 2006 IEEE International Symposium on Workload Characterization.

[6]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[7]  Abdul Al-Azzawi,et al.  Photonics: Principles and Practices , 2006 .

[8]  M.K. Emsley,et al.  High speed resonant cavity enhanced Ge photodetectors on Si reflecting substrates for 1550 nm operation , 2004, 2004 IEEE International Topical Meeting on Microwave Photonics (IEEE Cat. No.04EX859).

[9]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[10]  ChenGuoqing,et al.  Predictions of CMOS compatible on-chip optical interconnect , 2007 .

[11]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[12]  M. Lipson,et al.  Low-power-consumption short-length and high-modulation-depth silicon electrooptic modulator , 2003 .

[13]  William J. Dally,et al.  Microarchitecture of a high radix router , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[14]  Alyssa B. Apsel,et al.  Leveraging Optical Technology in Future Bus-based Chip Multiprocessors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[15]  Doron Rubin,et al.  40Gb/s Ge-on-SOI waveguide photodetectors by selective Ge growth , 2008, OFC/NFOEC 2008 - 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference.

[16]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[17]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[18]  Christopher Batten,et al.  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[19]  William J. Dally,et al.  Technology-Driven, Highly-Scalable Dragonfly Topology , 2008, 2008 International Symposium on Computer Architecture.

[20]  J. Tatum.  VCSELs for 10 GB/s optical interconnects , 2001, 2001 IEEE Emerging Technologies Symposium on BroadBand Communications for the Internet Era. Symposium Digest (Cat. No.01EX508).

[21]  Doug Burger,et al.  Implementation and Evaluation of On-Chip Network Architectures , 2006, 2006 International Conference on Computer Design.

[22]  P. Kapur,et al.  Comparisons between electrical and optical interconnects for on-chip signaling , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

[23]  Michal Lipson,et al.  All-optical switching on a silicon chip. , 2004, Optics letters.

[24]  Luca P. Carloni,et al.  Photonic networks-on-chip: Opportunities and challenges , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[25]  William J. Dally,et al.  Flattened Butterfly Topology for On-Chip Networks , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[26]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[27]  Amit Kumar,et al.  NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[28]  Mark A. Franklin,et al.  Gemini: An Optical Interconnection Network for Parallel Processing , 2002, IEEE Trans. Parallel Distributed Syst..

[29]  S. Mikhrin,et al.  Quantum dot laser with 75 nm broad spectrum of emission. , 2007, Optics letters.

[30]  A. R. Kovsh,et al.  Error-free 10 Gbit/s transmission using individual Fabry-Perot modes of low-noise quantum-dot laser , 2007 .

[31]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[32]  Qianfan Xu,et al.  12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators. , 2007, Optics express.

[33]  K.L. Shepard,et al.  Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication , 2007, IEEE Journal of Solid-State Circuits.

[34]  T. M. Pinkston,et al.  Design considerations for optical interconnects in parallel computers , 1994, First International Workshop on Massively Parallel Processing Using Optical Interconnections.

[35]  Prabhat Kumar,et al.  Exploring concentration and channel slicing in on-chip network router , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[36]  Chita R. Das,et al.  Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[37]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[38]  A. Kumary,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007 .

[39]  B. Jalali,et al.  Silicon photonics , 2006, IEEE Microwave Magazine.

[40]  William J. Dally,et al.  Cost-Efficient Dragonfly Topology for Large-Scale Systems , 2009, IEEE Micro.

[41]  B. Jalali,et al.  Silicon Photonics , 2006, Journal of Lightwave Technology.

[42]  Ahmed Louri,et al.  An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs) , 2004, IEEE Transactions on Parallel and Distributed Systems.

[43]  William J. Dally,et al.  Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.