Electrostatic discharge in semiconductor devices: an overview

Electrostatic discharge (ESD) is an event that sends current through an integrated circuit (IC). This paper reviews the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response, and (4) device failure. Topics reviewed are charge generation mechanisms, models for ESD charge transfer, electrical conduction mechanisms, and device damage mechanisms leading to circuit failure.

[1]  J. G. Smith,et al.  ESD Sensitivity and Latency Effects of some HCMOS Integrated Circuits , 1984 .

[2]  W. Fichtner,et al.  Layout optimization of an ESD-protection n-MOSFET by simulation and measurement , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[3]  T. J. Sanders,et al.  Statistical modeling of hot-electron and ESD induced degradation in non-isothermal device , 1997, Proceedings of the UGIM Symposium, Microelectronics Education for the Future. Twelfth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.97CH36030).

[4]  R. N. Rountree.  ESD protection for submicron CMOS circuits-issues and solutions , 1988, Technical Digest., International Electron Devices Meeting.

[5]  J. M. Soden,et al.  I/sub DDQ/ testing and defect classes-a tutorial , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[6]  T. W. Hughes,et al.  Properties of high voltage stress generated traps in thin silicon oxides , 1995, Proceedings of 1995 IEEE International Reliability Physics Symposium.

[7]  D. Wunsch,et al.  Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages , 1968 .

[8]  J. Bernier,et al.  ESD improvements for familiar automated handlers , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[9]  Sung-Mo Kang,et al.  Electrical overstress and electrostatic discharge , 1995 .

[10]  Sang U. Kim.  ESD induced gate oxide damage during wafer fabrication process , 1993 .

[11]  J. Reiner,et al.  Latent gate oxide defects caused by CDM-ESD , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[12]  S. Wolf,et al.  Silicon Processing for the VLSI Era , 1986 .

[13]  G. B. Kenney,et al.  Fusing Mechanism of Nichrome-Linked Programmable Read-Only Memory Devices , 1976, 14th International Reliability Physics Symposium.

[14]  Guido Groeseneken,et al.  Analysis of HBM ESD testers and specifications using a fourth-order lumped element model , 1994 .

[15]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[16]  William D. Greason,et al.  Latent effects due to ESD in CMOS integrated circuits: review and experiments , 1993 .

[17]  Dante M. Tasca,et al.  Pulse Power Failure Modes in Semiconductors , 1970 .

[18]  George Brian Kenney.  The fusing mechanism of NiCr resistors in programmable read-only memory devices. , 1975 .

[19]  K. Okada,et al.  CDM ESD test considered phenomena of division and reduction of high voltage discharge in the environment , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[20]  Christian Russ,et al.  ESD protection elements during HBM stress tests: further numerical and experimental results , 1995 .

[21]  Kueing-Long Chen,et al.  Electrostatic discharge protection for one micron CMOS devices and circuits , 1986, 1986 International Electron Devices Meeting.

[22]  Chih-Tang Sah,et al.  Degradation of bipolar transistor current gain by hot holes during reverse emitter-base bias stress , 1996 .

[23]  M. Honda,et al.  New approaches to indirect ESD testing , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[24]  L. R. Avery.  Electrostatic discharge - Mechanisms, protection techniques, and effects on integrated circuit reliability , 1984 .

[25]  Zdenek Kucerovsky,et al.  Experimental determination of ESD latent phenomena in CMOS integrated circuits , 1992 .

[26]  J.E. Vinson.  NiCr fuse reliability-a new approach , 1994, Conference Record Southcon.

[27]  Tomomitsu Satake.  Electromigration failure in NiCr thin‐film stripes , 1973 .

[28]  Gadi Krieger.  Nonuniform ESD current distribution due to improper metal routing , 1992 .

[29]  C. M. Melliar-Smith,et al.  Failure of Small Thin Film Conductors Due to High Current-Density Pulses , 1978, 16th International Reliability Physics Symposium.

[30]  Sung-Mo Kang,et al.  Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  J. Bernstein,et al.  Short-time failure of metal interconnect caused by current pulses , 1993, IEEE Electron Device Letters.

[32]  A. Olney.  A combined socketed and non-socketed CDM test approach for eliminating real-world CDM failures , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[33]  L. R. Avery.  A review of electrostatic discharge mechanisms and on-chip protection techniques to ensure device reliability , 1990 .

[34]  D.W. Greve,et al.  Programming mechanism of polysilicon resistor fuses , 1982, IEEE Transactions on Electron Devices.

[35]  D. J. Dumin,et al.  Wearout and Breakdown in Thin Silicon Oxide , 1995 .

[36]  O.J. McAteer.  Pulse Evaluation of Integrated Circuit Metallization as an Alternative to SEM , 1977, 15th International Reliability Physics Symposium.

[37]  J. Bernier,et al.  Die level CDM testing duplicates assembly operation failures , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[38]  M. Haunschild,et al.  Very-fast transmission line pulsing of integrated structures and the charged device model , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[39]  Sung-Mo Kang,et al.  Modeling and simulation of hot-carrier-induced device degradation in MOS circuits , 1993 .

[40]  Chenming Hu,et al.  Electrical breakdown in thin gate and tunneling oxides , 1985, IEEE Transactions on Electron Devices.

[41]  G. Theodore Dangelmayer,et al.  Design for electrostatic-discharge (ESD) protection in telecommunications products , 1990, AT&T Technical Journal.

[42]  G. S. Peter Castle,et al.  The Effects of Electrostatic Discharge on Microelectronic Devices A Review , 1984, IEEE Transactions on Industry Applications.

[43]  P. Chaparala,et al.  A new physics-based model for time-dependent-dielectric-breakdown , 1995, IEEE 1995 International Integrated Reliability Workshop. Final Report.

[44]  R. Holzner,et al.  A new ESD protection concept for VLSI CMOS circuits avoiding circuit stress , 1992 .

[45]  D. S. Campbell,et al.  Thermal failure in semiconductor devices , 1990 .

[46]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[47]  Miryeong Song,et al.  Quantifying ESD/EOS latent damage and integrated circuit leakage currents , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[48]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[49]  J. L. Davidson,et al.  Fusing Mechanism of Nichrome Thin Films , 1976, 14th International Reliability Physics Symposium.

[50]  A. Neugroschel,et al.  Accelerated reverse emitter-base bias stress methodologies and time-to-failure application , 1996, IEEE Electron Device Letters.

[51]  H. Gieser,et al.  Very fast transmission line pulsing of integrated structures and the charged device model , 1998, IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C.

[52]  Herman Maes,et al.  Influence of tester, test method, and device type on CDM ESD testing , 1995 .

[53]  W. D. Brown.  Semiconductor Device Degradation by High Amplitude Current Pulses , 1972 .