A Distortion Compensating Flash Analog-to-Digital Conversion Technique

We present a flash ADC design technique that compensates for static nonlinearity of the up-front track-and-hold circuit, so that high speed and high linearity can be obtained at the same time. The proposed technique functions in synergy with a new background comparator offset correction scheme. The excess quantization noise generated due to the background autozero process is derived. We demonstrate the efficacy of our techniques with measurement results for a 160 MSPS 6-bit flash converter designed in a 0.35-mum CMOS process. The ADC consumes 50 mW from a 3.3 V power supply and has an 5.3 effective number of bits (ENOB) at Nyquist

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