Compact Model of Carbon Nanotube Transistor and Interconnect

A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both I-V and C-V characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8× faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.

[1]  D. Pulfrey,et al.  Examination of the high-frequency capability of carbon nanotube FETs , 2008 .

[2]  H. Wong,et al.  Fabrication and Characterization of Carbon Nanotube Interconnects , 2007, 2007 IEEE International Electron Devices Meeting.

[3]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[4]  Yu Cao,et al.  Compact modeling of carbon nanotube transistor for early stage process-design exploration , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[5]  H. Wong,et al.  Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels , 2007, IEEE Transactions on Electron Devices.

[6]  H.-S. Philip Wong,et al.  First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier , 2006, 2006 International Electron Devices Meeting.

[7]  Ali Javey,et al.  Carbon Nanotubes: From Growth, Placement and Assembly Control to 60mV/decade and Sub-60 mV/decade Tunnel Transistors , 2006, 2006 International Electron Devices Meeting.

[8]  H. Wong,et al.  Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[9]  Kaushik Roy,et al.  Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  S. Roche,et al.  A simple drain current model for Schottky-barrier carbon nanotube field effect transistors , 2006, cond-mat/0610882.

[11]  K. Roy,et al.  Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure , 2006, IEEE Transactions on Electron Devices.

[12]  E. Pop,et al.  Electrical and thermal transport in metallic single-wall carbon nanotubes on insulating substrates , 2006, cond-mat/0609075.

[13]  H. Wong,et al.  Analysis of the Frequency Response of Carbon Nanotube Transistors , 2006, IEEE Transactions on Nanotechnology.

[14]  H. Wong,et al.  A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors , 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

[15]  D. Pulfrey,et al.  Switching-speed calculations for Schottky-barrier carbon nanotube field-effect transistors , 2006 .

[16]  B. Paul,et al.  Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits , 2006, IEEE Electron Device Letters.

[17]  Mark S. Lundstrom,et al.  Nanoscale Transistors: Device Physics, Modeling and Simulation , 2005 .

[18]  P. Avouris,et al.  High-performance dual-gate carbon nanotube FETs with 40-nm gate length , 2005, IEEE Electron Device Letters.

[19]  Phaedon Avouris,et al.  The role of metal-nanotube contact in the performance of carbon nanotube field-effect transistors. , 2005, Nano letters.

[20]  Kaustav Banerjee,et al.  Performance analysis of carbon nanotube interconnects for VLSI applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[21]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[22]  Kaushik Roy,et al.  A circuit-compatible model of ballistic carbon nanotube field-effect transistors , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  J. Kavalieros,et al.  High-/spl kappa//metal-gate stack and its MOSFET characteristics , 2004, IEEE Electron Device Letters.

[24]  P. McEuen,et al.  Electron-Phonon Scattering in Metallic Single-Walled Carbon Nanotubes , 2003, cond-mat/0309641.

[25]  S. Hareland,et al.  Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[26]  Mark S. Lundstrom,et al.  A numerical study of scaling issues for Schottky-barrier carbon nanotube transistors , 2003, IEEE Transactions on Electron Devices.

[27]  David L. Pulfrey,et al.  Towards a compact model for Schottky-barrier nanotube FETs , 2002, 2002 Conference on Optoelectronic and Microelectronic Materials and Devices. COMMAD 2002. Proceedings (Cat. No.02EX601).

[28]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[29]  J. Tersoff,et al.  Carbon Nanotubes as Schottky Barrier Transistors , 2002, cond-mat/0207397.

[30]  C. Dekker,et al.  Transport through the interface between a semiconducting carbon nanotube and a metal electrode , 2002, cond-mat/0206436.

[31]  S. Datta,et al.  Performance projections for ballistic carbon nanotube field-effect transistors , 2002 .

[32]  P. McEuen,et al.  Single-walled carbon nanotube electronics , 2002 .

[33]  C. Hu,et al.  A comparative study of advanced MOSFET concepts , 1996 .

[34]  J. Welser,et al.  Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors , 1994, IEEE Electron Device Letters.

[35]  Suman Datta,et al.  High- /Metal-Gate Stack and Its MOSFET Characteristics , 2004 .

[36]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[37]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[38]  L. B. Ebert.  Science of fullerenes and carbon nanotubes , 1996 .

[39]  M. C. Jeng,et al.  A physical model for MOSFET output resistance , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[40]  Chenming Hu,et al.  Electrical breakdown in thin gate and tunneling oxides , 1985, IEEE Transactions on Electron Devices.