Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis

A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period

[1]  Masakazu Shoji,et al.  Theory of CMOS Digital Circuits and Circuit Failures , 1992 .

[2]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[3]  M. A. Cirit.  Characterizing a VLSI standard cell library , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[4]  W. Roethig.  Library characterization and modeling for 130 nm and 90 nm SoC design , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[5]  David Blaauw,et al.  Modeling Flip Flop Delay Dependencies in Timing Analysis , 2003 .

[6]  D. Patel.  CHARMS: characterization and modeling system for accurate delay prediction of ASIC designs , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[7]  R. W. Phelps.  Advanced library characterization for high-performance ASIC , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.