An Approach to System-level Design for Test

In this chapter we will describe a Design-for-Test (DfT) methodology for systems-on-chip. We have developed a hybrid Built-In Self-Test (BIST) approach, where the test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated offline and stored in the system. We have analyzed the aspects related to the cost calculation of such a hybrid BIST approach and will propose a test cost minimization strategy for single-core designs. We have then extended the same approach for multi-core designs and developed a test time minimization methodology under tester memory constraints. We will demonstrate the applicability and efficiency of the proposed approach for cores with different core-level DfT structures and for systems with different system-level test architectures.

[1]  Makoto Sugihara,et al.  Analysis and minimization of test time in a combined BIST and external test approach , 2000, DATE '00.

[2]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[3]  Nur A. Touba,et al.  Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[4]  Janusz Rajski,et al.  Decompression of test data using variable-length seed LFSRs , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[5]  Raimund Ubar,et al.  Test cost minimization for hybrid BIST , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Kuen-Jong Lee,et al.  Broadcasting test patterns to multiple circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[8]  Vishwani D. Agrawal,et al.  A Tutorial on Built-In Self-Test, Part 2: Applications , 1993, IEEE Des. Test Comput..

[9]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[10]  Petru Eles,et al.  Test Time Minimization for Hybrid BIST of Core-Based Systems , 2003, 2003 Test Symposium.

[11]  Raimund Ubar,et al.  Using Tabu Search Method for Optimizing the Cost of Hybrid BIST , 2001 .

[12]  Solomon W. Golomb,et al.  Shift Register Sequences , 1981 .

[13]  Raimund Ubar,et al.  A hybrid BIST architecture and its optimization for SoC testing , 2002, Proceedings International Symposium on Quality Electronic Design.

[14]  Hans-Joachim Wunderlich,et al.  Mixed-Mode BIST Using Embedded Processors , 1998, J. Electron. Test..

[15]  Fred W. Glover,et al.  Future paths for integer programming and links to artificial intelligence , 1986, Comput. Oper. Res..

[16]  Dhiraj K. Pradhan,et al.  A novel pattern generator for near-perfect fault-coverage , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[17]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[18]  Raimund Ubar,et al.  Hybrid BIST optimization for core-based systems with test pattern broadcasting , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

[19]  Raimund Ubar,et al.  Fast test cost calculation for hybrid BIST in digital systems , 2001, Proceedings Euromicro Symposium on Digital Systems Design.