An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H

An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step.

[1]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[2]  Hae-Seung Lee,et al.  A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  Sang-Gug Lee,et al.  A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS , 2009, 2009 Proceedings of ESSCIRC.

[4]  Geert Van der Plas,et al.  A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Soon-Jyh Chang,et al.  A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process , 2009, 2009 Symposium on VLSI Circuits.

[6]  Sanroku Tsukamoto,et al.  A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).