Constraint Analysis for DSP Code Generation Manuscript received April 1, 1998; revised August 27, 1998. This paper was recommended by Associate Editor G. Borriello. Publisher Item Identifier S 0278-0070(99)00810-6.

[1]  Raymond Reiter,et al.  Scheduling Parallel Computations , 1968, J. ACM.

[2]  Gert Goossens,et al.  Chess: retargetable code generation for embedded DSP processors , 1994, Code Generation for Embedded Processors.

[3]  Alexander Aiken,et al.  Resource-Constrained Software Pipelining , 1995, IEEE Trans. Parallel Distributed Syst..

[4]  Monica S. Lam,et al.  RETROSPECTIVE : Software Pipelining : An Effective Scheduling Technique for VLIW Machines , 1998 .

[5]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[6]  B. Ramakrishna Rau,et al.  Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing , 1981, MICRO 14.

[7]  B. Ramakrishna Rau,et al.  Register allocation for software pipelined loops , 1992, PLDI '92.

[8]  Pierre G. Paulin,et al.  Flexware: A flexible firmware development environment for embedded systems , 1994, Code Generation for Embedded Processors.

[9]  Pierre G. Paulin,et al.  DSP design tool requirements for embedded systems: A telecommunications industrial perspective , 1995, J. VLSI Signal Process..

[10]  Bart Mesman,et al.  A constraint driven approach to loop pipelining and register binding , 1998, Proceedings Design, Automation and Test in Europe.

[11]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  J.L. van Meerbergen,et al.  Constraint analysis for DSP code generation , 1997, Proceedings. Tenth International Symposium on System Synthesis (Cat. No.97TB100114).

[13]  Rainer Leupers,et al.  Retargetable Code Generation Based on Structural Processor Description , 1998, Des. Autom. Embed. Syst..

[14]  Guang R. Gao,et al.  Minimizing register requirements under resource-constrained rate-optimal software pipelining , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[15]  Joos Vandewalle,et al.  Loop Optimization in Register-Transfer Scheduling for DSP-Systems , 1989, 26th ACM/IEEE Design Automation Conference.

[16]  Alexandre E. Eichenberger,et al.  Optimum modulo schedules for minimum register requirements , 1995 .

[17]  Alice C. Parker,et al.  Tutorial on high-level synthesis , 1988, DAC '88.

[18]  Jochen A. G. Jess,et al.  Efficient code generation for in-house DSP-cores , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.