A robust multi-bit soft-error immune SRAM cell for low-power applications

[1]  S. Birla,et al.  Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices , 2022, Int. J. Circuit Theory Appl..

[2]  M. Gholipour,et al.  Improved read/write assist mechanism for 10‐transistor static random access memory cell , 2022, Int. J. Circuit Theory Appl..

[3]  M. Gholipour,et al.  Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications , 2022, Circuits, Systems, and Signal Processing.

[4]  M. Gholipour,et al.  Robust transmission gate-based 10T subthreshold SRAM for internet-of-things applications , 2022, Semiconductor Science and Technology.

[5]  M. Gholipour,et al.  A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology , 2022, Arabian Journal for Science and Engineering.

[6]  M. Gholipour,et al.  A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins , 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  M. Gholipour,et al.  A 9T high-stable and Low-Energy Half-Select-Free SRAM Cell Design using TMDFETs , 2022, Analog Integrated Circuits and Signal Processing.

[8]  M. Gholipour,et al.  Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM , 2022, Microelectron. J..

[9]  R. Paily,et al.  Half‐selection disturbance free 8T low leakage SRAM cell , 2022, Int. J. Circuit Theory Appl..

[10]  M. Gholipour,et al.  A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology , 2022, Circuits, Systems, and Signal Processing.

[11]  M. Gholipour,et al.  A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications , 2022, Int. J. Circuit Theory Appl..

[12]  Morteza Gholipour,et al.  Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design , 2021, Int. J. Circuit Theory Appl..

[13]  Morteza Gholipour,et al.  Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications , 2021, Int. J. Circuit Theory Appl..

[14]  Vishal Sharma,et al.  A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes , 2020, Analog Integrated Circuits and Signal Processing.

[15]  M. Gholipour,et al.  A variation-aware design for storage cells using Schottky-barrier-type GNRFETs , 2020 .

[16]  Seong-Ook Jung,et al.  One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Rohit Lorenzo,et al.  Single bit-line 11T SRAM cell for low power and improved stability , 2020, IET Comput. Digit. Tech..

[18]  Wing-Hung Ki,et al.  A highly stable reliable SRAM cell design for low power applications , 2020 .

[19]  Wing-Hung Ki,et al.  Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications , 2020, IEEE Transactions on Electron Devices.

[20]  Santosh Kumar Vishvakarma,et al.  An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network , 2019, Microelectron. J..

[21]  Soumitra Pal,et al.  Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications , 2019, IET Circuits Devices Syst..

[22]  Santosh Kumar Vishvakarma,et al.  Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications , 2019, AEU - International Journal of Electronics and Communications.

[23]  Kari Halonen,et al.  A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes , 2018, Int. J. Circuit Theory Appl..

[24]  S. Chouhan,et al.  A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications , 2018, Analog Integrated Circuits and Signal Processing.

[25]  S. Chouhan,et al.  A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications , 2018, Analog Integrated Circuits and Signal Processing.

[26]  Mohd. Hasan,et al.  Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis , 2018, IEEE Transactions on Device and Materials Reliability.

[27]  Manoj Sachdev,et al.  A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology , 2018, IEEE Journal of Solid-State Circuits.

[28]  Santosh Kumar Vishvakarma,et al.  Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design , 2017, IEEE Transactions on Semiconductor Manufacturing.

[29]  Jongsun Park,et al.  Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  Mohd. Hasan,et al.  Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory , 2017, Microelectron. J..

[31]  Pinaki Mazumder,et al.  A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS , 2017, Integr..

[32]  Hanwool Jeong,et al.  Power-Gated 9T SRAM Cell for Low-Energy Operation , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[33]  Hidehiro Fujiwara,et al.  A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications , 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[34]  James E. Stine,et al.  A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

[35]  Soumitra Pal,et al.  9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue , 2016, IEEE Transactions on Device and Materials Reliability.

[36]  Mohd. Hasan,et al.  Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Volkan Kursun,et al.  Low power and robust memory circuits with asymmetrical ground gating , 2016, Microelectron. J..

[38]  Sied Mehdi Fakhraie,et al.  A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[39]  Chien-Yu Lu,et al.  A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[40]  Jun Zhou,et al.  Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[41]  Ming-Hsien Tu,et al.  40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[42]  Samar K. Saha,et al.  Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design , 2014, IEEE Access.

[43]  Ching-Te Chuang,et al.  Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[44]  Kwen-Siong Chong,et al.  An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[45]  Chien-Yu Lu,et al.  A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing , 2012, IEEE Journal of Solid-State Circuits.

[46]  Mohd. Hasan,et al.  A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell , 2012, Microelectron. Reliab..

[47]  Kaushik Roy,et al.  Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[48]  Kaushik Roy,et al.  A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications , 2011, IEEE Transactions on Circuits and Systems for Video Technology.

[49]  Zhi-Hui Kong,et al.  An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[50]  Massimo Alioto,et al.  Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[51]  Mohammad Sharifkhani,et al.  An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[52]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[53]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[54]  Magdy A. Bayoumi,et al.  Low-Power Cache Design Using 7T SRAM Cell , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[55]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[56]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[57]  S. Narendra,et al.  Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[58]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[59]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[60]  Mohd. Hasan,et al.  Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications , 2018 .

[61]  Ahmed M. Eltawil,et al.  AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement , 2017, IET Circuits Devices Syst..

[62]  Mathias Beike,et al.  Digital Integrated Circuits A Design Perspective , 2016 .

[63]  Chien-Yu Lu,et al.  A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance , 2013, 2013 IEEE International SOC Conference.

[64]  A.P. Chandrakasan,et al.  Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits , 2008, IEEE Transactions on Electron Devices.