A system level integration design for MPEG layer III audio decoder

MPEG Layer III audio decoding algorithms are involved in several complex-coding techniques and therefore it is difficult to design efficient dedicated architecture. We present a semi-ASIC architecture for an MPEG Layer III audio decoder. The MPEG Layer III algorithms can be divided into two types of operations. With an embedded RISC core and the two dedicated processing units, each type of operation can be performed efficiently. The decoder is designed based on the approaches of simplicity and low cost while meeting the high-efficiency requirements.

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