Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design

This paper presents a via-programmable expanded universal logic gate in MOS current-mode logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the first via mask, while metal3 and higher levels are used for cell-to-cell interconnections. Thus the cell is suitable for a structured ASIC design methodology. The circuit was used to create a functional cell library which can implement a wide range of functions. The cells are simulated to characterize delays, and a design strategy is proposed for large scale integration

[1]  Yusuf Leblebici,et al.  Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[2]  Yusuf Leblebici,et al.  Sub-70ps Full Adder in MOS Current-Mode Logic Using 0.18um CMOS Technology , 2004 .

[3]  Maitham Shams,et al.  Implementation of MCML universal logic gate for 10 GHz-range in 0.13 /spl mu/m CMOS technology , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Masakazu Yamashina,et al.  An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors , 1992 .

[5]  S. Bruma Impact of on-chip process variations performance on MCML [MOS current mode logic] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[6]  Gang Xu,et al.  CMP aware shuttle mask floorplanning , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[7]  Elizabeth J. Brauer,et al.  Low noise MCML prefix adders using 0.18 µm CMOS technology , 2004, Circuits, Signals, and Systems.

[8]  Paolo Ienne,et al.  Design of Low-Power DPA-Resistant Cryptographic Functional Units for Pervasive Computing , 2005 .