Analytical transient response and propagation delay model for nanoscale CMOS inverter

This paper presents a new analytical propagation delay model for nanoscale CMOS inverters. By using a non-saturation current model, the analytical input-output transfer responses and propagation delay model are derived. The model is used for calculating inverter delays for different input transition times, load capacitances and supply voltages. Delays predicted by the proposed model are in good agreement with those of transistor level simulation results from SPICE, with accuracy of 3% or better.

[1]  Atsushi Kurokawa,et al.  Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies , 2007, 2007 Asia and South Pacific Design Automation Conference.

[2]  Spiridon Nikolaidis,et al.  Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices , 1998, IEEE J. Solid State Circuits.

[3]  X. Zhou,et al.  An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation , 2002, Microelectron. Reliab..

[4]  S. Sapatnekar,et al.  A New Class of Convex Functions for Delay Modeling and Its Application to the Transistor Sizing Problem , 2000 .

[5]  Anas A. Hamoui,et al.  An analytical model for current, delay, and power analysis of submicron CMOS logic circuits , 2000 .

[6]  Nicholas C. Rumin,et al.  Inverter models of CMOS gates for supply current and delay evaluation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Yong-Bin Kim,et al.  An Accurate Analytical Propagation Delay Model of Nano CMOS Circuits , 2007 .

[8]  David Blaauw,et al.  Transistor-Specific Delay Modeling for SSTA , 2008, 2008 Design, Automation and Test in Europe.

[9]  Francis Balestra,et al.  On the drain current saturation in short channel MOSFETs , 2006, Microelectron. J..

[10]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[11]  L.G. Johnson,et al.  A Novel Delay Model of CMOS VLSI Circuits , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[12]  Yu Hen Hu,et al.  Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  J R Burns,et al.  SWITCHING RESPONSE OF COMPLEMENTARY SYMMETRY MOS TRANSISTOR LOGIC CIRCUITS , 1964 .

[15]  Seung-Ho Jung,et al.  Short circuit power estimation of static CMOS circuits , 2001, ASP-DAC '01.

[16]  Kjell Jeppson,et al.  Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay , 1994 .

[17]  Juan Bautista Roldán,et al.  A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot , 1998 .

[18]  José Luis Rosselló,et al.  An analytical charge-based compact delay model for submicrometer CMOS inverters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[20]  C. Y. Roger Chen,et al.  An efficient gate delay model for VLSI design , 2007, 2007 25th International Conference on Computer Design.

[21]  N. C. Rumin,et al.  Simultaneous delay and maximum current calculation in CMOS gates , 1992 .

[22]  S. Dutta,et al.  A comprehensive delay model for CMOS inverters , 1995 .

[23]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.

[24]  Maurizio Zamboni,et al.  A comprehensive submicrometer MOST delay model and its application to CMOS buffers , 1997 .