Novel cell array noise cancelling design scheme for stacked type MRAM with NAND structured cell

In this paper novel cell array noise cancelling design scheme considering memory cell array noise for stacked type NAND MRAM has been newly described. Memory cell array noise which is inherent to stacked type NAND MRAM is newly analyzed. This noise for read operation of 48mV is almost equal to the signal to selected WL of 50mV during read operation. For realizing the cell array noise cancelling the adjacent WLs in the adjacent NAND structure has been successfully used. Circuit design and pattern design of newly proposed row decoder and noise cancelling circuit are described. Using the novel design scheme stable read operation can be achieved with only area penalty of 2.2%. Proposed novel scheme is promising candidates for realizing stable operation of stacked type NAND MRAM.

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