EFFICIENTLINE-BASEDVLSIARCHITECTUREFOR 2-DLIFTINGDWT

DWT hasbeenthebasis ofimagecompression, suchasin JPEG2000. Thispaper proposes anovel VLSIarchitecture that performs line-based DWT using alifting scheme. The architecture consists ofrowprocessors, column processors, an intermediate bufferanda control module.The intermediate buffer iscomposedofFIFOsto store temporary results ofhorizontal filters. Thecontrol module schedules theoutput ofwavelet coefficients toexternal memorywiththepriority fromhightolow.Horizontal filtering andvertical filtering aresimultaneous, andall levels ofDWT areprocessed parallel. Thepresented architecture finishes multi levels of9/7DWT inoneimage transmission time. Meanwhile, itdecreases significantly memoryusedandhardware resource required. This architecture issuitable forvarious real-time image/video applications.