3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver

Since the invention of radio, superheterodyne has been the architecture of choice for receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker noise, time-varying dc offsets, in-band LO leakage and sensitivity to 2nd-order intermodulation are simply avoided. Unfortunately, the high IF requires high-quality-factor (Q) band-pass filters for image rejection, which cannot be easily integrated in CMOS. This forced the CMOS receivers to migrate to zero (or low) IF and suffer from the abovementioned problems. Recently, there have been attempts to revisit the high IF operation by exploiting N-path filtering [1] and a combination of a discrete-time (DT) band-pass charge-sharing filtering with feedback filtering [2]. Here, we propose a superheterodyne RX architecture with full DT operation using only gm stages, switches and capacitors. The transfer function is accurate and controlled by the clock frequency and precise capacitor ratios.