Electrostatic discharge in semiconductor devices: protection techniques

Electrostatic discharges (ESDs) are everywhere-in our homes and businesses. Even the manufacturers of the electronics experience ESD failures in their factories. Electronic devices are sensitive to ESD. ESD results in failure of our computers, calculators, and car phones. There are ways to protect these sensitive components. This paper looks at ESD protection from a two-pronged approach: reducing the likelihood of having an ESD event and improving the robustness of the devices themselves. The first approach focuses on reducing the amount of charge that is developed and controlling the redistribution of any charges that are developed The second approach reviews ways to improve the circuit robustness by improving individual circuit elements and by adding additional elements for charge flow control and voltage clamping.

[1]  W. D. Mack,et al.  New ESD protection schemes for BiCMOS processes with application to cellular radio designs , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[2]  Kueing-Long Chen,et al.  Electrostatic discharge protection for one micron CMOS devices and circuits , 1986, 1986 International Electron Devices Meeting.

[3]  Gregg D. Croft Transient supply clamp with a variable RC time constant , 1998 .

[4]  J. Bernier,et al.  ESD improvements for familiar automated handlers , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[5]  Charvaka Duvvury,et al.  A synthesis of ESD input protection scheme , 1992 .

[6]  G. Theodore Dangelmayer,et al.  Design for electrostatic-discharge (ESD) protection in telecommunications products , 1990, AT&T Technical Journal.

[7]  R. N. Rountree ESD protection for submicron CMOS circuits-issues and solutions , 1988, Technical Digest., International Electron Devices Meeting.

[8]  R. Bellens,et al.  Study Of The ESD Behavior Of Different Clamp Configurations In A 0.35/spl mu/m Cmos Technology , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[9]  P. Niles,et al.  Diffused resistors characteristics at high current density levels-analysis and applications , 1989 .

[10]  William D. Greason,et al.  Electrostatic discharge: a charge driven phenomenon , 1992 .

[11]  Xin Yi Zhang,et al.  Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits , 1996, Proceedings of International Reliability Physics Symposium.

[12]  R. Saini,et al.  Human hand/metal ESD and its physical simulation , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[13]  Carlos H. Díaz,et al.  Bi-modal triggering for LVSCR ESD protection devices☆ , 1995 .

[14]  S.H. Cohen,et al.  An improved input protection circuit for C-MOS/SOS arrays , 1978, IEEE Transactions on Electron Devices.

[15]  J.R.M. Luchies,et al.  Fast turn-on of an NMOS ESD protection transistor: measurements and simulations , 1995 .

[16]  Juin J. Liou,et al.  Electrostatic discharge in semiconductor devices: an overview , 1998, Proc. IEEE.

[17]  L. R. Avery A review of electrostatic discharge mechanisms and on-chip protection techniques to ensure device reliability , 1990 .

[18]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[19]  G. Groeseneken,et al.  Recommendations to further improvements of HBM ESD component level test specifications , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[20]  W.R. Anderson,et al.  ESD protection under wire bonding pads , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[21]  S. Voldman,et al.  A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[22]  Loren W. Linholm,et al.  Electrostatic Gate Protection using an Arc Gap Device , 1973 .

[23]  C. Duvvury,et al.  EOS/ESD analysis of high-density logic chips , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[24]  Bernard G. Carbajal,et al.  A successful HBM ESD protection circuit for micron and sub-micron level CMOS , 1993 .

[25]  D. Robinson-Hahn ESD flooring: an engineering evaluation , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[26]  C. Duvvury,et al.  The impact of technology scaling on ESD robustness and protection circuit design , 1995 .

[27]  Timothy J. Maloney,et al.  Novel clamp circuits for IC power supply protection , 1995 .

[28]  H. Hyatt,et al.  The resistive phase of an air discharge and the formation of fast risetime ESD pulses , 1993 .

[29]  A. Steinman,et al.  Developing an exit charge specification for production equipment , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[30]  O.J. McAteer Pulse Evaluation of Integrated Circuit Metallization as an Alternative to SEM , 1977, 15th International Reliability Physics Symposium.

[31]  D. C. Wunsch The Application of Electrical Overstress Models to Gate Protective Networks , 1978, 16th International Reliability Physics Symposium.

[32]  Gregg D. Croft ESD protection using a variable voltage supply clamp , 1995 .

[33]  A. Amerasekera,et al.  Thermal analysis of the fusion limits of metal interconnect under short duration current pulses , 1996, 1996 International Integrated Reliability Workshop Final Report.

[34]  H. Uchida,et al.  Control of static charge on personnel in an electronics working area , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[35]  C. Hu,et al.  Characterization of VLSI circuit interconnect heating and failure under ESD conditions , 1996, Proceedings of International Reliability Physics Symposium.

[36]  G. Theodore Dangelmayer ESD program management : a realistic approach to continuous, measurable improvement in static control , 1999 .

[37]  J. Bernstein,et al.  Short-time failure of metal interconnect caused by current pulses , 1993, IEEE Electron Device Letters.

[38]  Timothy J. Maloney,et al.  Protection of high voltage power and programming pins , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[39]  Timothy J. Maloney,et al.  Integrated circuit metal in the charged device model: bootstrap heating, melt damage, and scaling laws , 1993 .

[40]  Chenming Hu,et al.  Internal ESD transients in input protection circuits , 1989 .

[41]  D.E. Swenson,et al.  Resistance to ground and tribocharging of personnel, as influenced by relative humidity , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[42]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[43]  R. Holzner,et al.  A new ESD protection concept for VLSI CMOS circuits avoiding circuit stress , 1992 .

[44]  M. Honda,et al.  New approaches to indirect ESD testing , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[45]  Kousuke Okuyama,et al.  A study of ESD protection devices for input pins discharge characteristics of diode, lateral bipolar transistor, and thyristor under MM and HBM tests , 1998, IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C.

[46]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[47]  J.A. Gonzalez,et al.  Mathematical modeling of electrostatic propensity of protective clothing systems , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.