The LHCb trigger system. Implementation & performance

The LHCb trigger has been recently described in a TDR submitted to the LHCC. This presentation describes shortly the main components of this three‐level system, a synchronous hardware Level‐0 followed by a software Level‐1 running at 1 MHz, and finally a High Level Trigger to bring the rate down to 200 Hz. A short summary of the expected performance on several benchmark channels is also given.