Towards Scalable BDD-Based Logic Synthesis

Towards Scalable BDD-Based Logic Synthesis Dennis Wu Masters of Science Graduate Department of Electrical and Computer Engineering University of Toronto 2005 The past decade of logic synthesis research has looked at using Binary Decision Diagrams (BDDs) as an alternative to the traditional sum-of-product representation of logic functions. When compared to the later, logic synthesis algorithms using BDDs have been shown to have significantly better scalability, however, the area quality produced has been poor. This thesis describes two new improvements to BDD-based logic synthesis. The first is a sharing extraction algorithm to improve area. The second is a logic folding approach, where equivalent logic transformations are shared to improve runtime. The algorithms are evaluated in a new logic synthesis tool called FBDD. Experimental results on the MCNC benchmarks show an average area savings of 21% and runtime improvements of 3 times, when compared to a state-of-the-art BDD based logic synthesis system.

[1]  Fabio Somenzi,et al.  CUDD: CU Decision Diagram Package Release 2.2.0 , 1998 .

[2]  Sharad Malik,et al.  Application of BDDs in Boolean matching techniques for formal logic combinational verification , 2001, International Journal on Software Tools for Technology Transfer.

[3]  Robert K. Brayton,et al.  Heuristic Minimization of BDDs Using Don't Cares , 1994, 31st Design Automation Conference.

[4]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[5]  Ingo Wegener,et al.  On the complexity of minimizing the OBDD size for incompletely specified functions , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Tsutomu Sasao,et al.  DECOMPOS : An integrated system for functional decomposition , 1998 .

[7]  Richard Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[8]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2000, DAC.

[9]  Valeria Bertacco,et al.  The disjunctive decomposition of logic functions , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[10]  J. Rajski,et al.  A method for concurrent decomposition and factorization of Boolean expressions , 1990, ICCAD 1990.

[11]  Giovanni De Micheli,et al.  Technology mapping for electrically programmable gate arrays , 1991, 28th ACM/IEEE Design Automation Conference.

[12]  Olivier Coudert,et al.  Verification of Synchronous Sequential Machines Based on Symbolic Execution , 1989, Automatic Verification Methods for Finite State Systems.

[13]  Bernd Steinbach,et al.  An algorithm for bi-decomposition of logic functions , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Srinivasa Rao Arikati,et al.  A signature based approach to regularity extraction , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[15]  Tsutomu Sasao,et al.  Fast Boolean matching under permutation using representative , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[16]  Giovanni Squillero,et al.  RT-Level ITC'99 Benchmarks and First ATPG Results , 2000, IEEE Des. Test Comput..

[17]  Carl Sechen,et al.  Efficient canonical form for Boolean matching of complex functions in large libraries , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[18]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[19]  Thomas Kutzschebauch,et al.  Regularity driven logic synthesis , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[20]  M. F.,et al.  Bibliography , 1985, Experimental Gerontology.

[21]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[22]  S. Yamashita,et al.  An Efficient Method for Generating Kernels on Implicit Cube Set Representations , 1999 .

[23]  K. Karplus.  Using if-then-else DAGs for multi-level logic minimization , 1989 .

[24]  Olivier Coudert,et al.  A unified framework for the formal verification of sequential circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.