Nanometer Technology Effects on Fault Models for IC Testing

Accepted methods for testing integrated circuits, such as the fault models examined here, require ongoing research and continual adaptation to accommodate increasing circuit size, growing defect subtlety, and less varied manufacturing processes.

[1]  Richard D. Eldred Test Routines Based on Symbolic Logical Statements , 1959, JACM.

[2]  K. C. Y. Mei,et al.  Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.

[3]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[4]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[5]  Robert C. Aitken Finding defects with fault models , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[6]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[7]  P. Nigh,et al.  An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[8]  Sreejit Chakravarty,et al.  Introduction to ID̳D̳Q̳ testing , 1997 .

[9]  T. W. Williams Testing in nanometer technologies , 1999, DATE '99.

[10]  Atul Patel,et al.  Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).