Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal
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K. Wostyn | J. Geypen | H. Bender | D. Mocuta | N. Collaert | A. Sibaja-Hernandez | L. Ragnarsson | R. Loo | J. Mitard | H. Arimura | J. Franco | S. Sioncke | J. Maes | Q. Xie | M. Givens | F. Tang | X. Jiang | G. Boccardi | D. Cott | W. Vanherle | E. Chiu | X. Lu