A Scalable FPGA-based Floating-Point Gaussian Filtering Architecture

This paper proposes a novel architecture for a scalable FPGA-based floating-point Gaussian filtering core. The core not only is able to accept floating-point kernels but also allows the kernels to be modified in both size and values at runtime. The proposed floating-point Gaussian filtering core is described with Verilog-HDL and is able to implement on various FPGA families. We schedule the operations of functional units inside the core in a pipeline model to improve performance. The core can be used for a 1D or a 2D Gaussian filtering with a simple wrapper. We conduct multiple experiments with various FPGA families. Experimental results show that our core can work at up to 224 MHz when implemented on a Xilinx Virtex 7 xc7vx485 device. Using this device, our core is able to perform a 2D Gaussian filtering for 40 or 11 7201280 images per second with a 3 3 or a 11 11 floating-point kernel, respectively

[1]  Markus Oeser,et al.  Video Based Intelligent Transportation Systems – State of the Art and Future Development , 2016 .

[2]  G. Deng,et al.  An adaptive Gaussian filter for noise reduction and edge detection , 1993, 1993 IEEE Conference Record Nuclear Science Symposium and Medical Imaging Conference.

[3]  Daniel Llamocca,et al.  Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing , 2014, TRETS.

[4]  Manuel Graña,et al.  Face Processing for Security: A Short Review , 2010, CISIS.

[5]  Yu Liu,et al.  A real-time video denoising algorithm with FPGA implementation for Poisson–Gaussian noise , 2014, Journal of Real-Time Image Processing.

[6]  Janarbek Matai,et al.  Design and Implementation of an FPGA-Based Real-Time Face Recognition System , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

[7]  Jongsun Park,et al.  Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications , 2018, IEEE Transactions on Circuits and Systems for Video Technology.

[8]  Mohsen Machhout,et al.  FPGA implementation of filtered image using 2D Gaussian filter , 2016 .

[9]  Jae Wook Jeon,et al.  A hardware architecture design for real-time Gaussian filter , 2014, 2014 IEEE International Conference on Industrial Technology (ICIT).

[10]  F. Talbi,et al.  Separable convolution gaussian smoothing filters on a xilinx FPGA platform , 2015, Fifth International Conference on the Innovative Computing Technology (INTECH 2015).

[11]  Yuzo Iano,et al.  Implementation of a fixed-point 2D Gaussian Filter for Image Processing based on FPGA , 2015, 2015 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA).

[12]  R. Schott,et al.  Efficient FPGA implementation of steerable Gaussian smoothers , 2012, Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST).

[13]  Sohail Iqbal,et al.  A Hardware Architecture for Difference of Gaussian Calculation in Image Feature Extraction , 2014, 2014 12th International Conference on Frontiers of Information Technology.

[14]  Carlo Tomasi,et al.  Good features to track , 1994, 1994 Proceedings of IEEE Conference on Computer Vision and Pattern Recognition.

[15]  Sami Khorbotly,et al.  A modified approximation of 2D Gaussian smoothing filters for fixed-point platforms , 2011, 2011 IEEE 43rd Southeastern Symposium on System Theory.

[16]  Shyan-Ming Yuan,et al.  A Vision-Based Driver Nighttime Assistance and Surveillance System Based on Intelligent Image Sensing Techniques and a Heterogamous Dual-Core Embedded System Architecture , 2012, Sensors.

[17]  John F. Canny,et al.  A Computational Approach to Edge Detection , 1986, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[18]  Paolo Prinetto,et al.  AIDI: An adaptive image denoising FPGA-based IP-core for real-time applications , 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).