Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ)

The integration of Magnetic Tunnel Junctions (MTJ) above CMOS circuits in embedded Magnetic RAM (MRAM) or Magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A complete simulation model for the hybrid MTJ/CMOS design is presented in this paper. Based on the recently demonstrated Spin-Transfer Torque (STT) writing approach which promises to lower the switching current down to ∼120uA, we have added to the previous static model the dynamic behaviors as well as the switching probability and the thermal effects. The model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform. Many experimental parameters are included in this model to improve the simulation accuracy. Simulations demonstrate that the model can be efficiently used to design hybrid MTJ/CMOS circuits.

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