A codesign virtual machine for hierarchical, balanced hardware/software system modeling

The Codesign Virtual Machine (CVM) is introduced as a next generation system modeling semantic. The CVM permits unrestricted system-wide software and hardware behaviors to be designed to a single scheduling semantic by resolving time-based (resource) and time-independent (state-interleaved) models of computation. CVM hierarchical relationships of bus and clock state domains provide a means of exploring hardware/software scheduling trade-offs to a consistent semantic model using top-down, bottom-up and iterative design approaches from a high system level to the machine implementation. State domain partitionings permit run-time software schedulers to be resolved with design time physical scheduling as peer- and hierarchically-related architectural abstractions which cut across functional boundaries. The resultant abstraction provides “component-less” paths to physical design with greater accommodation of shared resource modeling. A simulation example is included.

[1]  Wayne Wolf,et al.  Communication synthesis for distributed embedded systems , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[2]  J. M. Paul,et al.  Peer-based multithreaded executable co-specification , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[3]  Donald E. Thomas,et al.  The Verilog hardware description language (4th ed.) , 1998 .

[4]  Wayne H. Wolf,et al.  Hardware/software co-synthesis with memory hierarchies , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[5]  Hugo De Man,et al.  CoWare—A design environment for heterogeneous hardware/software systems , 1996, EURO-DAC '96/EURO-VHDL '96.

[6]  Kiyoung Choi,et al.  Optimistic distributed timed cosimulation based on thread simulation model , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[7]  Bruce P. Douglass,et al.  Doing hard time: developing real-time systems with uml , 1999 .

[8]  W. Wolf,et al.  Hardware/software co-synthesis with memory hierarchies , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[9]  G. De Micheli,et al.  SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[10]  Luciano Lavagno,et al.  Hardware-software co-design of embedded systems: the POLIS approach , 1997 .

[11]  William J Edwards,et al.  Doing Hard Time , 1994 .

[12]  G. Borriello,et al.  Communication synthesis for distributed embedded systems , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[13]  Giovanni De Micheli,et al.  SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C , 1998, ICCAD.

[14]  Bran Selic Turning clockwise: using UML in the real-time domain , 1999, CACM.

[15]  Donald E. Thomas,et al.  The Verilog® Hardware Description Language , 1990 .

[16]  Donald E. Thomas,et al.  Frequency interleaving as a codesign scheduling paradigm , 2000, CODES '00.

[17]  Edward A. Lee,et al.  OVERVIEW OF THE PTOLEMY PROJECT JULY 6 , 1999 , 1999 .

[18]  David B. Skillicorn,et al.  Models and languages for parallel computation , 1998, CSUR.

[19]  said Cinderella Turning Clockwise : Using UML in the Real-Time Domain , 1999 .

[20]  Gaetano Borriello,et al.  A geographically distributed framework for embedded system design and validation , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[21]  Frank Vahid,et al.  SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design , 1998, IEEE Trans. Very Large Scale Integr. Syst..