A proposed symmetric and balanced 11-T SRAM cell for lower power consumption
暂无分享,去创建一个
[1] R.H. Dennard,et al. An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.
[2] H. Pilo,et al. An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management , 2009, IEEE Journal of Solid-State Circuits.
[3] Ajay Kumar Singh,et al. A proposed SRAM cell for low power consumption during write operation , 2009 .
[4] T. Sakurai,et al. 90% write power-saving SRAM using sense-amplifying memory cell , 2004, IEEE Journal of Solid-State Circuits.
[5] C. Radens,et al. A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing , 2008, IEEE Journal of Solid-State Circuits.
[6] Sani R. Nassif,et al. The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[7] Takayasu Sakurai,et al. 90% write power-saving SRAM using sense-amplifying memory cell , 2004 .
[8] Feipei Lai,et al. Zero-aware asymmetric SRAM cell for reducing cache power in writing zero , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] Lawrence T. Clark,et al. Leakage Controlled Read Stable Static Random Access Memories , 2008, J. Comput..
[10] Massoud Pedram,et al. Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology , 2008, IEEE Trans. Very Large Scale Integr. Syst..
[11] M. Yabuuchi,et al. Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access , 2009, IEEE Journal of Solid-State Circuits.
[12] Rajiv V. Joshi,et al. Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics , 2009, IEEE Journal of Solid-State Circuits.