Parametrizable VLSI Application Specific Datapaths for High Speed Data Communications

The processing requirements for high speed datacommunication systems (symbol rates in excess of 5 MHz)are beyond the capabilities of programmable devices suchas DSP chips and FPGAs. Designers of such systems have traditionally incurred the highnone recurring engineering (NRE) costs and longdevelopment times associated with custom ASICimplementations. In this paper we highlight an emergingtrend in the development of parametrizable, high speeddatapaths for application in data communications. Suchcircuits can deliver the high throughputs associatedwith traditional ASIC implementations while at the same time provide the user with the ability tovary key system parameters, or even redefine the circuitfunctionality among a finite number of alternatives.They have the potential to significantly reduce the cost of implementing high-speed datacommunication systems by reducing the NRE costs.Moreover, the ability to use the same piece of hardwarein a large number of different systems provides further price reductions due to economies of scale. Inorder to bring out key concepts associated with thedesign of such systems, the paper provides an in-depthdescription of three sample circuits. They are: (a) A versatile rake-receiver architecture foruse in DSSS-CDMA based systems; (b) A highlyreconfigurable baseband processing engine forapplication in a host of systems based on single carriermodulation; and (c) A highly versatile beamformingIC.

[1]  B. Daneshrad,et al.  Direct digital frequency synthesis using a modified CORDIC , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[2]  S. Onoe,et al.  Wideband-CDMA radio control techniques for third-generation mobile communication systems , 1997, 1997 IEEE 47th Vehicular Technology Conference. Technology in Motion.

[3]  T. Saramaki,et al.  Interpolation filters with arbitrary frequency response for all-digital receivers , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[4]  C. W. Farrow,et al.  A continuously variable digital delay element , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[5]  Mamoru Sawahashi,et al.  Coherent DS-CDMA: promising multiple access for wireless multimedia mobile communications , 1996, Proceedings of ISSSTA'95 International Symposium on Spread Spectrum Techniques and Applications.

[6]  Woo Jin Oh,et al.  Implementation of programmable multiplierless FIR filters with powers-of-two coefficients , 1995 .

[7]  H. Samueli,et al.  A VLSI architecture for a universal high-speed multirate FIR digital filter with selectable power-of-two decimation/interpolation ratios , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[8]  Milos D. Ercegovac,et al.  Low-power accumulator (correlator) , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[9]  Lars Erup,et al.  Interpolation in digital modems. II. Implementation and performance , 1993, IEEE Trans. Commun..

[10]  S. Haykin,et al.  Adaptive Filter Theory , 1986 .

[11]  Seung Chan Bang,et al.  Performance analysis of a wideband CDMA system for FPLMTS , 1997, 1997 IEEE 47th Vehicular Technology Conference. Technology in Motion.