A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.

[1]  Asad A. Abidi Noise in active resonators and the available dynamic range , 1992 .

[2]  A. Abidi,et al.  A 1GHz CMOS analog-front-end for a partial-response read channel , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  A.S. Sedra,et al.  Analog MOS integrated circuits for signal processing , 1987, Proceedings of the IEEE.

[4]  Asad A. Abidi,et al.  CMOS active filter design at very high frequencies , 1990 .

[5]  Y.P. Tsividis,et al.  Widely programmable high-frequency continuous-time filters in digital CMOS technology , 2000, IEEE Journal of Solid-State Circuits.

[6]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[7]  Yong Wang,et al.  A 700 Mb/s BiCMOS read channel integrated circuit , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[8]  Jan W. M. Bergmans,et al.  A class of data-aided timing-recovery schemes , 1995, IEEE Trans. Commun..

[9]  N. Nazari A 500 Mb/s disk drive read channel in 0.25 /spl mu/m CMOS incorporating programmable noise predictive Viterbi detection and trellis coding , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  Asad A. Abidi,et al.  A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel , 2001 .

[11]  H. Shafiee Timing recovery for sampling detectors in digital magnetic recording , 1996, Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications.

[12]  G. David Forney,et al.  Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference , 1972, IEEE Trans. Inf. Theory.

[13]  Tzuwang Pan,et al.  A trellis-coded E/sup 2/PRML digital read/write channel IC , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[14]  Asad A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS , 2001 .

[15]  Asad A. Abidi,et al.  A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels , 1996 .

[16]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.