This paper presents studies performed in engineering high-k metal gate stacks by using capping layers containing Group IIA and IIIB elements. Both high-k gate dielectric (HfO2) and capping materials, namely, the oxides of barium, lanthanum and yttrium are deposited by atomic layer deposition (ALD) to offer superior process control and flexibility. Position specific insertion of cap layers into the gate stack is studied and the device tradeoffs are highlighted. The magnitude of Vt shift is correlated to the electronegativity of the cap layer species and its relative position in the gate stack. For a given cap position, BaO provides the maximum Vt shift, followed by La2O3 and Y2O3 caps. Ozone based ALD processes are shown to adversely impact Tinv scaling due to the re-growth of the interface layer between the high-k and the silicon substrate. Significant improvements in Tinv scaling are obtained by migrating to a water based ALD process.